ADSP-BF532

GENERAL DESCRIPTION

The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Black fin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC like microprocessor instruction set, and single instruction, multiple data (SIMD) multimedia capabilities into a single instruction set architecture.

FEATURES

Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter
RISC-like register and instruction model for ease of programming and compiler- friendly support
Advanced debug, trace, and performance monitoring
0.85 V to 1.30 V core VDD with on-chip voltage regulation
1.8 V, 2.5 V, and 3.3 V compliant I/O
160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP packages

MEMORY

Up to 148K bytes of on-chip memory:
16K bytes of instruction SRAM/Cache
Up to 64K bytes of instruction SRAM
Up to32K bytes of data SRAM/Cache
Up to32K bytes of data SRAM
4K bytes of scratchpad SRAM
Memory management unit providing memory protection
External memory controller with glueless support for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI® and external memory

PERIPHERALS

Parallel peripheral interface PPI/GPIO, supporting ITU-R 656 video data formats
Two dual-channel, full duplex synchronous serial ports, supporting eight stereo I2S channels
Four memory-to-memory DMAs
Eight peripheral DMAs
SPI-compatible port
Three 32-bit timer/counters with PWM support
Real-time clock and watchdog timer
32-bit core timer
Up to 16 general-purpose I/O pins (GPIO)
UART with support for IrDA®
Event handler
Debug/JTAG interface
On-chip PLL capable of 0.5� to 64� frequency multiplication