GTLP18T612

General Description

The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.

Features

■ Bidirectional interface between GTLP and LVTTL logic levels
■ Edge Rate Control to minimize noise on the GTLP port
■ Power up/down high impedance for live insertion
■ External VREF pin for receiver threshold
■ BiCMOS technology for low power dissipation
■ Bushold data inputs on A Port eliminates the need for external pull-up resistors for unused inputs
■ LVTTL compatible Driver and Control inputs
■ Flow-through architecture optimizes PCB layout
■ Open drain on GTLP to support wired-or connection
■ A-Port source/sink −24 mA/+24 mA
■ B-Port sink capability +50 mA
■ D-type flip-flop, latch and transparent data paths