MT46V64M8P-6T F

Functional Description

The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.

Features

• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400)
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto refresh
– 64ms, 8192-cycle(Commercial and industrial)
– 16ms, 8192-cycle (Automotive)
• Self refresh (not available on AT devices)
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
• tRAS lockout supported (tRAP = tRCD)