FS6005

Description

The FS6050 family of CMOS clock fanout buffer ICs are designed for high-speed motherboard applications, such as Intel Pentium® II PC100-based systems with 100MHz SDRAM.
Up to eighteen buffered, non-inverting clock outputs are fanned-out from one clock input. Individual clocks are skew matched to less than 250ps at 100MHz. Multiple power and ground supplies reduce the effects of supply noise on device performance.
Under I2C-bus control, individual clock outputs may be turned on or off. An active-low output enable is available to force all the clock outputs to a tristate level for system testing.

Features

• Generates up to eighteen low-skew, non-inverting clocks from one clock input
• Supports up to four SDRAM DIMMs
• Uses either I2C-bus or SMBus serial interface with Read and Write capability for individual clock output control
• Output enable pin tristates all clock outputs to facilitate board testing
• Clock outputs skew-matched to less than 250ps
• Less than 5ns propagation delay
• Output impedance: 17Ω at 0.5VDD
• Serial interface I/O meet I2C specifications; all other I/O are LVTTL/LVCMOS-compatible
• Five differerent pin configurations available:
• FS6050: 18 clock outputs in a 48-pin SSOP
• FS6051: 10 clock outputs in a 28-pin SOIC, SSOP
• FS6053: 13 clock outputs in a 28-pin SOIC
• FS6054: 14 clock outputs in a 28-pin SOIC